The present invention is related to a PCI bus, and more particularly to a PCI bus in which transaction sizes may be specified.
Computer systems include a number of components that need to exchange data. For example, a typical computer system includes a processor, memory, hard drive, etc. Busses are used to connect the components in a computer system. For example, the processor and memory in a typical computer system are interconnected by a system or frontside bus. Peripheral devices such as network cards, sound cards, modems, disk controllers, etc may be connected to the computer system by a Peripheral Component Interconnect (PCI) bus. Peripheral devices in this example can access system memory across the PCI bus, through a bus bridge and across the system bus. Busses such as the PCI bus have a great affect on the apparent speed of a computer system, with multiple devices trying to communicate over a single bus at the same time and with inherent limitations of the bus design affecting data throughput.
One such limitation is that the legacy PCI bus protocol includes no notion of transaction sizing. A memory map 10 for data transactions on a PCI bus is established as shown in FIG. 1. Memory address ranges 12, 14 and 16 are set aside for data flowing upstream and downstream, and the PCI bus master is able to perform memory read transactions within the memory map 10 using FRAME#, IRDY#, AD, and CMD/BE# signals, but it cannot indicate the amount of data to be transmitted in a transaction. In many systems the PCI master 20 is behind one or more bridges 22 and 24 as illustrated in FIG. 2. When the PCI master 20 needs to read data, for example from system memory in a root complex 26, it will make a read request. The read request works its way up the hierarchy with a latency penalty at each bridge 22 and 24. When the request reaches a bridge 22 to a non-PCI protocol (for example PCI-Express) the bridge 22 will have to guess at the amount of read data to request. The guess is implementation specific with the only hint on the PCI bus 30 being the use of Memory Read, Memory Read Line, or the Memory Read Multiple commands. These commands give very little guidance regarding the actual amount of data to read when the request wants many cachelines of data. The completer 26 of the read request will return the amount of data that was “guessed” by the bridge 22. The data will pass down the hierarchy to the PCI master 20 again incurring a latency delay at each bridge 22 and 24 in the path.
If the read data returned was too large the excess data has to be discarded. The PCI bridge specification requires that all read data not consumed by the master 20 in one PCI bus transfer be discarded. For example if the PCI master 20 wanted A words of data and the “guessed” amount of data was B (where B is greater than A) words then the data that the PCI master did not want (B−A words) will be discarded by the bridge 22. The discarded data will have wasted bandwidth on the path from the source of the data 26 to the final bridge 22 before the PCI master 20.
If the read data returned was too little the PCI master 20 will have to make multiple reads to obtain the needed data. Each read will incur the latency of the read request going to the source of the data and the delay of the data being returned to PCI master 20. When there are multiple PCI masters wishing to read data simultaneously the penalties become even worse. For example, in a multi-agent system on a PCI bus 30, all the agents (e.g., 20) try to access the bus 30 and an arbitrator attempts to give each agent a share in round robin fashion. Thus, an agent 20 may require multiple requests 32 and 34 before the required data is obtained. Each read will incur the loop latency penalty of the request 32 and 34 going up the hierarchy and the read data flowing down back to the PCI master 20. In many systems the latency penalty of the request going up and the data coming down is much greater than the time it takes to transfer the data on the PCI bus 30. In this type of an environment breaking up the read into multiple requests will significantly reduce the read throughput.
Thus, for at least the aforementioned reason, there exists a need in the art for an improved PCI bus.